The I2C Clock Speed – Why Accuracy Doesn’t Matter
In a synchronous serial transmission like an RS232 communication the clock speed is predetermined. Since the receiver does not get an explicit clock signal it has to rely on the accuracy of the sender’s timing. Any deviation is almost fatal as it may cause errors sooner or later. While there is technology available to keep such communication in sync even if the so called baud rate slightly drifts the overall approach is to keep that rate constant and accurate.
This has the advantage of predictable transfer timing but it adds the obvious requirement of keeping that constant rate. This is why baud rate calculators are found all over the internet.
On synchronous transmissions like the I2C bus the situation is much more relaxed. The clock is transmitted by the sender and the receiver is always able to synchronize with that clock. I2C defines several speed grades but the term baud rate is quite unusual in this context.
The speed grades (standard mode: 100 kbit/s, full speed: 400 kbit/s, fast mode: 1 mbit/s, high speed: 3,2 Mbit/s) are maximum ratings. Compliant hardware guaranties that it can handle transmission speed up to the maximum clock rate specified by the mode.
This does not imply that a transmission may not take place at any lower speed or even at a somewhat variable bit rate.
In fact, a bus master does not even have full control over the actual timing. The reason for this is simple. The I2C bus uses open drain technology. The bus is kept on a high level and writing to the bus means to pull its level to ground. Depending on bus termination, serial resistors, capacitance, cable length, bus voltage and other factors this process of pulling down the level and releasing it takes some time. It is therefore good practice for any device to read back the logic level of a modified line (both clock and data) before proceeding with further actions.
A master will write a zero on the bus by first enabling the circuit to pull the bus low, then read back the state of the line and then proceed with the next step.
As a consequence a master set to clock at 100 kHz will most likely produce a lower speed on the bus. As the impact of electrical latency increases with higher clock rates this effect shows more with higher speeds.
The I2C bus is intended for inter-IC communication and this usually means small data packets. Since the timing can never be determined exactly and the transmitted information is often short the accuracy of the bus clock is of very little relevance in most applications.
To be on the safe side it is – in case of doubt – a much better idea to keep the maximum bit rate below the maximum rating at any time rather than exceeding it occasionally.