The addressing scheme for high speed transfers differs from the normal addressing procedure.
After the start condition, a so-called master code is transmitted ‘00001XXX’, followed by a mandatory not-acknowledge bit. The master code is sent in Fast- or Standard-mode (this is with at most 400bkit/s).
The three lowest bits are used to identify different I2C masters on the same bus – each one has its unique identifier. During transmission of the master code, arbitration takes place, so that only the winning master can perform the following high speed transfer.
The master codes are selectable by the designer and allow up to eight high speed masters to be connected in one system (master code ‘00001000’ should be reserved for test and diagnostic purposes).
After the acknowledge phase following the master code, the high speed transfer begins with a repeated start condition, followed by the slave address and the succeeding data, just like in Fast or Standard mode, but with a higher bit rate.
The high speed mode remains active until a stop condition is transmitted, on which the connected high speed devices switch back to slow transmission rates like Fast or Standard mode.
The picture below shows the beginning of a high speed transfer.