Making the fast mode faster

The I2C fast mode was originally specified to run at 400 kbit/s. So what keeps people from ignoring this 400 kbit/s limit and running the same bus with the same logic at higher speeds? There are a couple of factors which limit the maximum speed on the bus. First, there’s the capacitance which introduces a rise time for the signals. As a “counter measure” the current on the bus can be increased by lowering the resistor values for the termination pull-ups.

Secondly, the bus has some timing tolerances and if the speed is increased these tolerances need to be more restrictive. The Fast-mode plus specification FM+ introduced by Philips Semiconductors (now: NXP) in April 2006 defines such a bus with a maximum speed of 1 Mbit/s. Unlike the high speed mode there is no additional logic to implement. Therefore, fast-mode plus devices are downward compatible with standard and fast-mode devices. In fact, many I2C slaves on the market like RAMs and EEPROMs will already tolerate higher bus frequencies.

The specification for FM+ is now part of the current I2C-bus specification and user manual (document UM10204 from NXP), available from NXP.