The I2C specification poses several requirements to I2C devices in order to ensure proper operation in different environments. The most important ones are:
- Both, SDA and SCL, must be open drain and must not be driven high by any device attached to the I2C bus.
- In most I2C buses, the low and high input voltage level thresholds of SDA and SCL must depend on Vcc. E.g. an SDA voltage level of 1.1 V will be interpreted as low in an I2C bus with Vcc = 5 V and as high in an I2C bus with Vcc = 1.2 V.
- The SCL and SDA signals must be sampled by Schmitt Trigger inputs, i.e. with a certain hysteresis.
- Spikes in SCL and SDA signals must be filtered up to a certain amount (only for full speed I2C).
- Setup and hold times; this includes a specified maximum SCL clock rate (100 kHz for normal speed, 400 kHz for full speed).
Most off-the-shelf standard I2C ICs fulfill these requirements while e.g. I2C software implementations in microcontrollers often do not. This does not necessarily need to be a problem as long as the environment does not require a feature that one of the devices on the I2C bus does not support, but has to be kept in mind when tracking down I2C bus-related problems.