During a master transmitter transfer, the slave suddenly does not acknowledge the bytes from the master anymore. This may happen directly after the address byte or later during the data transfer stage. Possible reasons are:
- The I2C slave could not correctly interpret the data on SDA because the SDA high or low-level voltages do not reach its appropriate input thresholds.
- The I2C slave missed an SCL cycle because the SCL high or low-level voltages do not reach its appropriate input thresholds.
- The I2C slave accidently interpreted a spike etc. as an SCL cycle.
With adequate serial resistors between master and slave, an analog shot of the signals at the slave’s SDA and SCL pins provides a clue whether the slave acknowledges and to which SCL clock pulse. The different SDA low levels due to the serial resistor make it possible to distinguish acknowledges from the slave from data bits from the master.