High Speed Mode

There are applications where the I2C transfer speed is a limiting factor. To allow for higher transmission rates while retaining a certain amount of compatibility Philips has introduced the HS I2C standard. Here are some details and particularities:

Electrical Characteristics

  • The high-speed variant of the I2C bus allows communication up to 3.4 Mbit per second.
  • Both, master and slave device must be highspeed-enabled in order to benefit from this increase.
  • High-speed IC devices are downward compatible allowing for mixed bus systems.
  • In order to shorten signal rise time HS mode master devices have a combination of an open-drain pull-down and current-source pull-up circuit on the SCL output.
  • HS IC masters can actually source current to the bus which is referred to as boosting.
  • This current source is enabled only (!) during HS operation and just for one master.
  • HS mode master devices generate a serial clock signal with a HIGH to LOW ratio of 1 to 2.
  • HS mode master devices can have a built-in bridge to separate lower speed devices from the bus during HS transfer. The main purpose of such bridge is to reduce the capacitive load on the bus and to avoid conflicts caused by low speed devices.

Transmission Format

A high-speed transmission starts up in full-speed mode, i.e. at max. 400 kbit.

High Speed

  • Start condition is sent
  • 8 bit ‘master code’ is sent at 400 kbit max
  • Master code is ‘not acknowledged’
  • Active master switches to high-speed communication
  • The ‘master code’ is a reserved value. 8 of them are available
  • Arbitration and clock synchronisation only take place during master code transmission, not during HS transfer
  • The current-source circuit is enabled after the transmission of the master code
  • The active master sends out a repeated start condition followed by the address of the desired slave
  • This address is acked or nacked
  • Transmission continues in the known manner
  • The current source circuit is disabled after each repeated start condition and after each ack or nack to give slaves a chance to stretch the clock
  • It is re-enabled once SCL has been released by all devices
  • All devices return to fast mode operation after a stop condition is sent
  • More details on the addressing scheme for high-speed transfers is available on this page.

Clock Stretching

Clock stretching during this mode has a special rule: It is only allowed after the ACK bit (and before the 1st bit of the next byte). Stretching between bits 2-9 is illegal because the edges of these bits are boosted with an additional current source. See I2C specification rev. 03 chapter 5.3.1 for further details.


The I2C HS-mode is rarely supported by I2C interfaces. Tracii XL 2.0 features this mode.