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In order to prevent address clashes, due to the limited range of the 7 bit addresses, a new 10 bit address scheme has been introduced. This enhancement can be mixed with 7 bit addressing and increases the available address range about ten times.

After the start condition, a leading '11110' introduces the 10 bit addressing scheme.

The last two address bits of the first byte concatenated with the eight bits of the second byte form the whole 10 bit address. Devices which only use 7 bit addressing simply ignore messages with the leading '11110'. 

The following picture shows the first two bytes of a transfer with a 10 bit address.

A master transmitter adresses the slave with two address bytes as described above with the RW-Bit='0' followed by data bytes from the master.

The master receiver transfer is only possible with a Combined Transfer due to the fact that the second address byte can only be transmitted, if the RW-Bit of the first address byte is '0'.

Hence the start of a master receiver transfer will be the same as a master transmitter transfer followed by a repeated start condition and the first byte of address byte with RW-Bit='1' (switching to slave transmitter mode). Please refer to the following master receiver sequence:

* Start condition

* First address byte, RW-Bit='0', ACK from the slave

* Second address byte, ACK from the slave

* Repeated start condition (no stop condition!)

* First address byte again, RW-Bit='1', ACK from the slave, slave switches to transmit mode

* Slave transmits data bytes, ACK from master

* After the last data byte the master sends a NACK

* Stop condition

 

Please consult the I2C specification for details.

 

 
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