A slave addressed by a master receiver transfer acknowledges the address byte and starts to send its data correctly, but suddenly all bytes send by the slave are 0xff.

• The I2C slave missed a SCL cycle because the SCL high or low level voltages do not suffice its appropriate input thresholds.
• The I2C slave accidently interpreted a spike etc. as a SCL cycle.

After having received the last byte during a master receiver transfer, the master leaves SDA high during the acknowledge clock cycle - this causes the slave not to send data any more, regardless whether a stop condition follows or not. Here, the slave is not synchronized any more with the master, and interprets a high SDA as a "not acknowledge" from the master.