It is assumed that the reader understands the protocol basics of I2C and is thus familiar with terms like I2C master and slave, (re-)start and stop conditions and acknowledges.

For details see the I2C specification V.2.1 from NXP, formerly Philips.

Note: High-speed I2C has additional aspects which are not addressed here.

The pictures shown in the following sections have been made with Tracii XL.

Chapter of this I2C primer:





	I2C Primer
I2C Bus I2C Primer Typical I2C Bus Setup How I2C Hardware Works Termination versus Capacitance Termination versus Serial Resistance Serial Resistances and Debugging Crosstalk between SDA and SCL Clock, Stretching, Arbitration Requirements Common Problems Obscure Problems Analysing Obscure Problems Addressing Auto Increment Clock Stretching Fast Mode Fast Mode Plus High Speed Mode I2C Interface Level Shifting Multi-Master References Repeated Start Condition Single-Master Slave Standard Mode Termination Voltage Level PMBus SMBus Imprint	In order to use the I2C bus properly and efficient, it is important to understand what happens in the hardware on electric level. This essay explains the hardware setup of an I2C bus the requirements for proper operation of the I2C bus how to find the cause for problems and how to solve them It is assumed that the reader understands the protocol basics of I2C and is thus familiar with terms like I2C master and slave, (re-)start and stop conditions and acknowledges. For details see the I2C specification V.2.1 from NXP, formerly Philips. Note: High-speed I2C has additional aspects which are not addressed here. The pictures shown in the following sections have been made with Tracii XL. Chapter of this I2C primer: Typical I2C Bus Setup How I2C Hardware Works Termination versus Capacitance Termination versus Serial Resistance Serial Resistances and Debugging Crosstalk between SDA and SCL Clock, Stretching, Arbitration Requirements Common Problems Obscure Problems Analysing Obscure Problems